Various memory configurations have been proposed to accomodate very high speed exchange of blocks of information between two processors. In such situations, traditional serial or parallel communication techniques are either too slow or too hardware intensive. On the other hand, dual port RAMs have been used successfully in those applications where the information is only occasionally changed and the speed of the two processors is not too disparate. The latter limitation is not a problem in RAM-to-RAM block transfer type systems, since each processor has separate access to its own RAM. However, in addition to doubling the size of the RAM, either considerable time or circuitry is required to actually accomplish the transfer. Using page swapping, the two processors can share a multiplexed address decode and data access network to achieve a very fast and efficient block transfer. However, after every update and swap operation, the updating processor must make the same update again in order to assure that the correct information will be available in both pages. The effective throughput of the updating processor can thus be significantly degraded.